1. Field of the Invention
The present invention generally relates to electronic circuits, and more specifically to the generation of reference voltages close to the circuit supply voltages.
An example of application of the present invention relates to analog-to-digital converters and to the generation of reference voltages defining the levels of states “0” and “1” of the bits. More generally, the present invention applies as soon as at least one reference voltage close to the level of a supply voltage is desired (for example, digital-to-analog converters and reference circuits for video signals).
2. Discussion of the Related Art
FIG. 1 is a schematic block diagram of an example of an analog-to-digital converter 1 (ADC) of the type to which the present invention applies. Such a converter is supplied by a D.C. voltage Vdd applied between two terminals 2 and 3 of circuit 1. In the example of FIG. 1, the converter has differential inputs. A differential signal Vin is applied between two input terminals 4 and 5 of the converter, which also receives two reference signals VrefP and VrefM on inputs 6 and 7. Reference signals VrefP and VrefM provide voltage levels around half the supply voltage Vdd/2. A sampling frequency is set by a clock signal Clk applied on a clock input 9. Circuit 1 provides a binary signal OUT over n bits on a series output or several parallel outputs 8.
FIG. 2 illustrates, with a voltage scale, the operation of the converter of FIG. 1. Voltages VrefP and VrefM range between levels Vdd and 0 on either side of median level Vdd/2. Difference ΔV between levels VrefP and VrefM defines the converter dynamics. The greater this interval, the better the signal-to-noise ratio of the converter. Gap g+ between voltage Vdd and voltage VrefP and gap g− between voltage VrefM and the ground (0) are linked to technological constraints of the circuit, as will be seen hereafter.
Within converter 1, reference signals VrefP and VrefM are applied to one or several elements operating as current sources, which absorb (on level VrefP) or provide (on level VrefM) a current depending on the work frequency of the converter and on the number of stages respectively providing states 0 and states 1.
After, the present invention will be described in relation with the generation of a single reference level VrefP close to positive level Vdd of the supply voltage. It should however be noted that it more generally applies to the generation of positive or negative reference signals, for example, in a differential application. Similarly, for simplification, reference will be made to a negative reference (level 0) corresponding to ground, knowing that it may be any positive or negative level lower than level Vdd.
FIG. 3 schematically shows a conventional example of a circuit for generating a reference voltage VrefP of the type to which the present invention applies. Voltage VrefP is provided by an N-channel MOS transistor MN1, connected between a line 2 of provision of voltage Vdd and a current source 11 connected to ground 3. Transistor MN1 and source 11 form the output stage of a transconductance amplifier 10 having a first input 14 receiving, through a resistor R1, a fixed reference voltage VBG linked to the technology (generally called bandgap voltage), and having a second input connected to ground. Internally, the first input is connected to an input amplifier 12(A). Output 13 of the circuit (drain of transistor MN1) is looped back on input 14 by a resistor R2. The respective values of resistors R1 and R2 set the value of level VrefP with respect to level VBG.
The assembly of FIG. 3 is generally called a “follower” assembly and its function is to provide the current necessary to the operation of the circuits connected downstream of terminal 13, while maintaining voltage level VrefP.
In applications where supply voltage Vdd is relatively low (less than 3 V, typically 2.5 V), it is difficult to maintain level VrefP close to level Vdd. Indeed, the operation of the follower of FIG. 3 requires a voltage of approximately 600 mV, or even 900 mV, to provide the gate-source voltage of transistor MN1 which imposes the voltage difference between terminal 2 and terminal 13. The drop out voltage of amplifier 12 adds to this gate-source problem. As a result, in practice, voltage level VrefP is around one volt. By applying the same circuit on the side of generation of level VrefM with respect to ground, it can be seen that a dynamic range of a few hundreds of millivolts is obtained for the converter, which is in practice insufficient. Accordingly, this solution is not adapted to such low supply voltages.
To bring level VrefP closer to level Vdd, the structure of the output stage is generally inverted by connecting a P-channel MOS transistor in series with a current source between terminals 2 and 3. However, this requires sizing this transistor to the worst operating case of the application, since it must support all of the current if the downstream circuit (the converter) absorbs no current.
FIG. 4 shows another conventional example of a follower circuit 20 for generating a reference voltage VrefP for an analog-to-digital converter 1. In FIG. 4, current source 15 to which converter 1 is equivalent, for reference voltage VrefP, has been illustrated in dotted lines. Input 4 of converter 1 is grounded by an external capacitor Cext has the function of stabilizing level VrefP. For simplification, only the output stage of the follower amplifier has been shown in FIG. 4. Of course, such an assembly also comprises a feedback (resistors R1 and R2) with input 14 of amplifier 20.
In the example of FIG. 4, a P-channel MOS transistor MP1 is controlled by input amplifier 12 of the assembly and is connected, by a current source 21, to the terminal of application of voltage Vdd. The fact of transferring the current source on the positive supply side enables avoiding the significant voltage drop linked to the gate-source voltage of the N-channel MOS transistor of FIG. 3. A second current source 22 connects the drain of transistor MP1 to ground 3 and this drain is connected to a third current source 23, mirror-assembled on current source 21. The mirror ratio generally is one and current source 22 is a fixed current source absorbing the sum of the currents provided by sources 21 and 22. For example, a first P-channel MOS transistor MP2 forming source 21 connects terminal 2 to the source of transistor MP1. Its gate is directly connected to that of a second transistor MP3 forming current source 23, the common gates being further connected to the drains of transistors MP1 and MP3. Such an assembly enables decreasing the size of MOS transistor MP1, since it does not carry continuously the maximum current (worst case) absorbed by downstream converter 1.
When converter 1 draws current (source 15), amplifier 12 reacts by increasing the gate voltage of transistor MP1. This results in opening transistor MP1 and mirror transistor MP2 then provides the converter with a current corresponding to the value set by source 21. Conversely, when the converter draws no current, transistor MP1 is on and the fixed current absorbed by source 22 is not only provided by transistor MP1, but also by transistor MP3.
As compared with the assembly of FIG. 3, the assembly of FIG. 4 enables reaching a voltage VrefP on the order of 2 volts for a voltage Vdd on the order of 2.2 volts (level Vdd decreased by approximately 0.2 V for the operation of transistor MP2).
By reproducing a similar assembly (based on N-channel transistors) on the negative terminal side (ground 3) of the power supply, a second reference level VrefM at approximately 0.2 V may be generated, which provides greater dynamic range at 1 V to the converter. Such a dynamic range is acceptable in most cases.
However, a disadvantage of the solution of FIG. 4 is that the current absorbed by source 22 remains set by the worst case of operation of the downstream-connected circuits and thus generates a significant power consumption. The output of such a reference voltage generator thus remains low.
Another disadvantage of the assembly of FIG. 4 is the nearly compulsory use of an external capacitor Cext between follower circuit 20 and converter 1. Two external capacitors are further necessary to stabilize the two reference levels VrefP and VrefM in the case of a differential system.
Such external capacitor(s) in practice have values of several microfarads, which makes them bulky. Further, the use of external capacitors generates other disturbances linked to the packages and to the connection terminals.